Effect of High Temperature Furnace Anneal to Element Diffusion in SIO₂-SI₃N₄ Stacks

Aiming at sloped profile post lateral etch of SiO<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> layers within the 5 tiers of SiO<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf>-Si<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</inf>N<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</inf>(ON) stacks, we added 700/800°C furnace anneal for 30 min in N<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> atmosphere of ON stacks before etch. Compared with non-anneal ON stacks, N concentration in SiO<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> increased and distribution is more uniform as expected. Furthermore, H content in SiO<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> layers also decreased from 2E20 to 1.5E20 atoms/cm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sup>, which is benefit to channel stability. SiO<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> later etch process was then performed on the post annealed ON stacks, slope-type profile was disappeared which prove N non-uniform diffusion result in sloped profile, provides valuable insights for the development of 3D DRAM technologies.