A Sige Channel Gate-All-Around Transistor Fabricated Using Novel Cyclic Self-Limiting Wet Etching Combined with SI Removal Process

In this work, a novel SiGe channel gate-all-around (GAA) transistor using a cyclic self-limiting wet etching process combined with Si removal process after dummy gate removal in the mainstream FinFET process is demonstrated in detail. The width of SiGe channel is narrowed from 20 nm to 6.5 nm and its mole fraction of Ge of SiGe channel can be increased from 31.8% to ~40%. Meanwhile, I<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DS</inf> of 382 μA/μm is obtained at V<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DS</inf> = V<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GS</inf> = -0.8V, with I<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</inf>/I<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OFF</inf> ratio of ~5.5e5 and SS of 76 mV/dec. These results prove that this novel process provides a potential solution to prepare the SiGe channel GAA transistor.