Advanced Verification Strategy for AHB-to-APB Bridge with Protocol-Aware Test Bench

This paper focuses on designing and verifying an AHB-to-APB bridge, a crucial Soc component enabling seamless communication between AHB and APB peripherals. Implemented in Verilog, the design ensures optimized hardware efficiency and functionality. Verification uses a UVM-based testbench, incorporating constrained-random stimulus, assertions, and protocol-aware strategies to identify corner-case bugs and validate boundary conditions. Functional and code coverage are meticulously tracked, with the aim of 96% coverage to ensure design reliability. Additionally, assertionbased verification enhances protocol compliance by validating correct behaviour under all conditions. The modular and scalable verification framework enables reusability across protocol converters and Soc components. This project ensures the robust operation of the AHB-to-APB bridge and contributes to efficient and reusable verification methodologies in modern Soc architectures.