Process Window Optimization for Gate Etch Process of 2D NAND

Two dimensional (2D) NAND has been used in applications such as industrial control systems and automotive electronics. Manufacturers working on further scale traditional planar NAND face significant challenges in processing high aspect ratio (HAR) structures. This paper focuses on the gate etch process of 2D NAND, presenting findings from a systematic investigation conducted using SEMulator3D<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">®</sup>, a 3D predictive modeling software. The analysis reveals that the formation mechanisms of two primary defects during the gate etch, active area (AA) pitting and fence defects, are intricately linked to the control of oxide-nitride-oxide (ONO) spacer height in the control gate (CG), ONO and floating gate (FG) etch processes. Furthermore, the defect process window is explored, highlighting the critical importance of both ONO/poly selectivity and poly etch amount control. Ensuring a proper balance is essential for managing spacer height effectively. During actual gate etch process tuning, pattern loading emerges as the most challenging issue, including the trade-offs between pitting, fencing and profile loading across different patterns. Effective strategies have been implemented to optimize the process window. The findings of this investigation not only reveal the key lesson learned for the control of AA pitting and fence defects, but also provide guidance for appropriate gate etch recipe design and process window optimization.