A DLL-TDC Circuit with Calibration Network
This paper introduces a DLL-TDC circuit with a calibration neural network to address the issue of uneven delay time distribution across each delay unit of the TDC. Following the integration of the DLL circuit into the TDC for the purpose of average calibration, this paper also proposes the construction of a neural network model which purpose of this is to calculate the accurate delay time of each delay unit. Furthermore, the neural network model can also replace the repetitive code density measurement work in order to complete bin-by-bin calibration. The neural network model has an accuracy rate of over $91 \%$.
Authors
- Chenxu Wang (ORCID: https://orcid.org/0000-0002-1337-682X)
- M. Xu (ORCID: https://orcid.org/0009-0008-4768-9067)
- Liang Han (ORCID: https://orcid.org/0000-0002-8281-9794)
- He Wen (ORCID: https://orcid.org/0000-0003-4181-4724)
- Yuehong Gong
- Min Luo (ORCID: https://orcid.org/0000-0003-3284-629X)
Institutions
- Shandong Jiaotong University (CN)
Publication Details
- Published
- 2025-03-21
- DOI
- https://doi.org/10.1109/iscait64916.2025.11010287
- Primary Topic
- Analog and Mixed-Signal Circuit Design
- Type
- article
- Field-Weighted Citation Impact
- 0.00