Design, Fabrication, and Process Optimization of Low-Voltage Super Junction TG MOSFET

This paper introduces a novel low-voltage Super Junction Trench Gate MOSFET (SJ TG MOSFET) device developed from a commercial TG MOSFET product in the 12-inch technology. This SJ TG MOSFET was investigated by TCAD simulation and characterized by experiments. A novel cost-effective method was employed to form a P-type pillar (PPL) in this work, which features multiple boron implantations. It was experimentally shown that both V<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">B</inf> of 102.23 V and R<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">sp</inf> of 49.41 mΩ•mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> were achieved in this low-voltage SJ TG MOSFET device. It was distinctly demonstrated that this SJ TG MOSFET was a competitive device in some low-voltage applications.