A Low-Power Multi-Core SNN Co-Processor with Subminiature Scalable Near-Memory MAC Module

In this paper, we present a multi-core brain-inspired co-processor based on binary spiking neural network (SNN). A multicore reconfigurable technique has been implemented and using adaptive router to realize flexible multicore interconnection and efficient parallel computing. A proximity matrix module based on binary encoding and XNOR coding is designed to reuse the matrix between data input, computation result recovery and data transfer. Thus, the 98.92 % reduction is achieved in efficiency of data computation and data transfer. The test chip for image recognition was fabricated and realized under 55nm COMS process. The results show that the chip consumes as low as 7.44 mW at 1.2 V/100 MHz with 96.92% recognition accuracy. Compared to the state-of-art works, more than 20.9% reduction in power consumption is obtained.