A 292.2-to-321.4-GHz Synchronized Source Generator With −58.7-dBc Spurious Tone and 136.7-fs _rms Integrated Jitter in 22-nm CMOS Technology

This article introduces a synchronized source generator operating from 292.2 to 321.4 GHz. It involves a millimeter-wave (mmW) phase-locked loop (PLL) cascaded with an <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$8\times $</tex-math> </inline-formula> frequency multiplier chain. A complementary ripple-neutralized phase detector (CRN-PD) is introduced in the PLL for ripple compensation during phase alignment, aiming to reduce the PLL spurious tone level. A calibration scheme enhances the robustness of ripple neutralization. The CRN-PD is further developed to support frequency and lock detection (LD). Another calibration scheme is introduced to capture the optimal locking point of the dynamic-latch-based prescaler, eliminating the need for external tuning. The source generator was implemented in a 22-nm CMOS technology, achieving −110.6- and −86.1-dBc/Hz phase noise at a 1-MHz offset, respectively, at 39.8 and 307.7 GHz, indicating the integrated jitter of 63.0 and 136.7 fs<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">rms</sub> (10 kHz–100 MHz). The spurious tone level is −58.7 dBc, normalized to 320 GHz. The signal source generates a peak output power of −8.6 dBm, and it consumes <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$216.2\sim 249.5$</tex-math> </inline-formula> mW of power from 0.9-/1.8-V power supplies.