A 16-to-30-Gb/s 1.03-pJ/b Baud-Rate Receiver With Referenceless CDR Employing Integrated Pattern Decoding Technique in 28-nm CMOS

This paper presents a referenceless baud-rate clock and data recovery (CDR) circuit with an integrated pattern decoding technique for fast frequency acquisition. The proposed CDR achieves baud-rate frequency acquisition without edge sampling clock phase by utilizing an integrator circuit. The proposed integrated pattern decoding technique divides 6-bit sequential patterns into 5 pattern groups. The patterns of each pattern group are detected from the specific frequency offsets. By applying larger weights to the pattern groups including the patterns detected at the higher frequency offset, the proposed referenceless CDR achieves fast frequency acquisition. Fabricated in a 28-nm CMOS technology, the CDR prototype occupies 0.039 mm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and consumes 30.77 mW at 30 Gb/s. From various initial clock frequency, the proposed CDR achieves a capture range from 16 Gb/s to 30 Gb/s. Thanks to the fast frequency acquisition ability of the proposed integrated pattern decoding technique, the worst frequency acquisition time at the data rate of 30 Gb/s is <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$3.7~\mu $</tex-math> </inline-formula>s. The CDR achieves a bit error rate (BER) of less than <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$10^{-12}$</tex-math> </inline-formula> and an energy efficiency of 1.03 pJ/b.