2D Mesh Topology in Clusters for Network-on-Chip Architecture at Large Scales

It is anticipated that the number of processing cores in chip multiprocessors and systems-on-chip will increase significantly shortly, soondue to Moore's law's continual growth. The task of efficiently and scalablely connecting the various parts of a multiprocessor device has grown more difficult. The network-on-chip (NoC) topologies that are now in use are suitable for small networks but not well-suited for big networks. Due to the longer routes needed to get to their destinations, sent packets inside a big NoC result in higher performance metrics like latency and power consumption. Therefore, creating a new topology suitable for large-size NoCs is required. In this study, we suggested an affordable network design that enhances end-to-end latency performance for large-scale NoCs. The RaMesh topology is made up of mesh network clusters. Additionally, a routing technique appropriate for this architecture was suggested. Altera ModelSim was used to simulate the RaMesh architecture for Verilog hardware models, along with mesh, torus, and clustered 2D mesh. Various network traffic scenarios and network sizes were used in the simulations. According to experimental data, RaMesh outperformed torus, clustered 2D mesh, and similar 2D mesh topologies. Additionally, RaMesh topology was compared to another clustered mesh topology for benchmarking. In comparison to mesh, torus, and clustered 2D mesh, the suggested topology had an average hop count that was at least 31% lower. Additionally, the average latency was reduced by at least 25% when compared to mesh, torus, and clustered 2D mesh.