Design and Analysis of an Approximate 8-Bit Multiplier Using Low Power Compressor

In modern digital systems, energy efficiency has become a crucial consideration, particularly in applications where power and area constraints are critical. This paper presents a novel 8-bit multiplier design utilizing approximate computing techniques to reduce the logic resource requirements, power consumption, and area, while maintaining a reasonable level of accuracy. The design incorporates Approximate Condition-based Majority Logic Compressors (ACMLC) and Compensator Approximate Compressors (CAC) for efficient multiplication. A detailed comparison of the existing method and the proposed method reveals that the proposed design achieves a reduction in LUT usage (from 86 to 70) and power consumption, both static and dynamic, with only a slight trade-off in accuracy. The proposed approach offers a promising solution for low-power and area-efficient multipliers, suitable for applications such as embedded systems, signal processing, and machine learning accelerators.