ENERGY-EFFICIENT MULTIPLIER DESIGN USING URDHVA TIRYAGBHYAM ALGORITHM AND APPROXIMATE COMPRESSORS

Efficient multiplier design is essential for enhancing the performance of digital systems, especially in applications demanding high-speed and low-power computations. This study presents a novel multiplier architecture based on the Vedic Urdhva Tiryagbhyam algorithm, integrated with approximate compressors for partial product addition using 5:3, 6:3, and 7:3 designs. The proposed method is evaluated against conventional stacker-based binary compressor designs. Experimental results reveal significant improvements: area utilization is reduced from 596 to just 56 Look-Up Tables (LUTs), static power consumption decreases from 0.823 W to 0.136 W, and dynamic power drops from 48.008 W to 15.363 W. These optimizations make the proposed architecture highly energy-efficient and suitable for resource-constrained digital systems. The results demonstrate the effectiveness of combining approximate computing with Vedic algorithms, offering a compelling solution for next-generation low-power, high-performance arithmetic applications.