A 40 GHz High-Image-Rejection LNA with a Switchable Transformer-Based Notch Filter in 65 nm CMOS

This article presents a low-noise amplifier (LNA) with high image rejection ratio (IRR) operating in the 5G millimeter-wave band using a 65 nm CMOS process. The circuit adopts an inter-stage notch filtering structure composed of a transformer and a switched capacitor array to achieve image suppression and impedance matching with no die area overhead. By adjusting the values of the switch capacitor array, the transmission zeros are positioned in the stopband while the poles are placed in the passband, thereby realizing image rejection. Furthermore, the number and distribution of poles under the both real and complex impedance conditions are analyzed. Moreover, the quality factor (<i>Q</i>) of the zero is derived to establish the relationship between <i>Q</i> and the image rejection ratio, guiding the optimization of both gain and IRR of the circuit design. Measurement results demonstrate that the LNA exhibits a gain of 18 dB and a noise figure (NF) of 4.4 dB at 40 GHz, with a corresponding IRR of 53.4 dB when the intermediate frequency (IF) is 6 GHz. The circuit demonstrates a 3 dB bandwidth from 36.3 to 40.7 GHz, with an IRR greater than 42 dB across this frequency range. The power consumption is 25.4 mW from a 1 V supply, and the pad-excluded core area of the entire chip is 0.13 mm².