Hot Carrier Suppression for Low <i>R</i>on Degradation in a Triple RESURF LDMOS

In this article, the three-phase ON-state resistance (<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">R</i><sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><roman>on</roman></sub>) degradation mechanisms are thoroughly investigated in a shallow trench isolation (STI)-based laterally diffused MOS (LDMOS). The charge-pump (CP) experiments and extensive simulations reveal that the initial <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">R</i><sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><roman>on</roman></sub> degradation is primarily dominated by hot-carrier injection (HCI) effects at the source-side bottom corner of STI. To solve it, a novel hot-carrier suppression (HCS) technique is proposed to modulate the electric fields and thereby suppress the HCI effects at this critical location. After optimization, the fabricated HCS LDMOS exhibits a significantly improved HCI immunity, with maximum <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">R</i><sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><roman>on</roman></sub> degradation limited to less than 0.75%, 0.62%, and 0.80% at <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i><sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><roman>gs</roman></sub> = 1, 3, and 5 V, respectively, reduced around 3.39%, 1.59%, and 2.45% when compared to the conventional LDMOS.