Secure Scan Architecture for Enhanced Testability and Resistance Against Side-Channel Attacks in Cryptographic ICs

Traditional scan-based Design for Testability (DFT) techniques give full visibility of internal nodes, which makes them vulnerable to side channel attacks where the confidential data is compromised. Physical attributes of power, timing, electromagnetic radiation, and fault responses are exploited by these attacks, which threaten intellectual property, secret keys, and chip information. In this paper, we address these vulnerabilities by introducing a novel secure scan architecture that protects against scan-based attacks. To ensure robust security from side channel attacks, brute force key attacks and unauthorized access, the proposed architecture utilizes Linear Feedback Shift Registers (LFSRs), shadow registers, and key based authentication mechanisms. A thorough evaluation of the countermeasures is conducted and a detailed comparison of Power, Performance, and Area (PPA) metrics versus Quality of Results (QoR) metrics such as coverage, area, runtime, and security checks, is presented. The proposed design attains high fault coverage of ~99.99%, reduces test patterns by ~1.81x, and lowers run time by ~5.45x. Moreover, the power consumption is reduced by ~50.9% while the area overhead is kept below ~2.17% to achieve resource efficient implementation. Architectural scalability analysis shows the flexibility of the architecture in terms of supporting different scan chain lengths, improved fault detection, and energy efficiency. These results prove the proposed secure scan architecture to be a very effective and resource optimized solution for advanced cryptographic and integrated circuit applications with a superior tradeoff between security, testability, and efficiency.