ML-Driven Transistor Self-Heating Analysis From TCAD to Large IP Circuits

To mitigate the increasing short-channel effects of miniaturization, the channel is wrapped increasingly with gate metal and insulating oxides to improve electrostatic control while worsening self-heating. Hence, self-heating has become a reliability concern and will increase in severity with more advanced nodes in the future (e.g., nanosheets), accelerating aging and shortening the transistor’s lifetime. Although standardized compact models include self-heating, their lumped nature abstracts the temperature gradient over the transistor’s cross-section. To this end, we have used TCAD to generate a distributed channel temperature map data set. We propose a technology-agnostic methodology for extracting localized temperature data on the circuit level using the trained machine learning model (with a mean error of 0.1 K). We explore our method to study self-heating in complex large circuits featuring over 3700 transistors. This includes foundries IPs like a complete high-performance SRAM-based register file. Our method provides the thermal map for every transistor and time step. The voltage and thermal traces are processed with an aging framework to estimate the expected aging more realistically. Using the proposed methodology reduces the conservative constant 50 mV threshold voltage shift to 31 mV, improving circuit performance through less pessimistic aging estimations. This unprecedented detailed analysis of self-heating at the large scale of the circuit will open new doors for designers to evaluate how self-heating propagates from transistors to circuits and impacts their reliability and lifetime.