A 10-Gb/s 3.6-pA/√ Hz Input Noise Optical Receiver in 28-nm CMOS
This brief presents a 10 Gb/s optical receiver frontend that aims to replace the traditional APD with transimpedance amplifier (TIA) with a cost-effective design combining a PIN-PD and a super low-noise TIA (S-TIA). The STIA employed in this study features both architecture and circuit innovation to reach the substantial noise reduction required. Additionally, an innovative on-chip integrated lownoise PD bias is proposed. According to the test results, the entire chip consumes 121 mW of power, achieves a gain of 92 dBΩ, a bandwidth of 5.3 GHz, an input noise of 259 nArms, and an input noise density of 3.6 pA/Hz. The receiver demonstrates an Optical Modulation Amplitude (OMA) of -26.2 dBm at 10 Gb/s with a Bit Error Rate (BER) of 1E-3.
Authors
- Li Geng (ORCID: https://orcid.org/0000-0003-4002-9281)
- Shuaizhe Ma (ORCID: https://orcid.org/0009-0004-7476-9522)
- Yifei Xia (ORCID: https://orcid.org/0009-0008-9637-6710)
- Ruixuan Yang (ORCID: https://orcid.org/0009-0001-0049-2645)
- X. Y. Shan
- Dan Li (ORCID: https://orcid.org/0000-0003-0721-3167)
- Yuye Yang
- Chuanhao Yu
- Xi Liu
- Shenlei Bao (ORCID: https://orcid.org/0009-0005-3779-4427)
- Binhao Wang (ORCID: https://orcid.org/0000-0002-4040-8444)
Institutions
- Xi'an Institute of Optics and Precision Mechanics (CN)
- State Key Laboratory of Transient Optics and Photonics
- Xi'an Jiaotong University (CN)
Publication Details
- Journal
- IEEE Transactions on Circuits & Systems II Express Briefs
- Published
- 2025-06-02
- DOI
- https://doi.org/10.1109/tcsii.2025.3575733
- Primary Topic
- Advancements in PLL and VCO Technologies
- Type
- article
- Field-Weighted Citation Impact
- 0.00
Funders
- National Natural Science Foundation of China