A 94.6 dB-SNDR 20 μW Extended-Counting Incremental ADC Based on Dynamic Amplifier With Gain Calibration

This paper presents a 1st-order extended-counting (EC) incremental analog-to-digital converter (IADC) based on dynamic amplifier (DA). The wide output swing and high gain requirement of the amplifier makes it infeasible to design an energy-efficient high-resolution EC IADC based on DA. Conventional gain-boosting methods, such as multi-stage and cascoding, suffer from the stability issue and limited output swing respectively. To solve this problem, a foreground gain calibration method is proposed for reducing the gain requirement by compensating the quantization error caused by the limited gain of DA. Additionally, a two-stage DA is proposed to achieve wide output swing and high energy-efficiency, which combines the floating-inverter-based amplifier (FIA) and the switched-inverter-based amplifier (SIA). SIA works as the 2nd stage, providing wide output swing while FIA as the 1st stage maintains the gain > 50 dB. A prototype of 1st-order EC IADC based on the proposed DA with gain calibration is fabricated in 180-nm CMOS technology. Operating under 1.8-V power supply, the EC IADC achieves a SNDR/DR of 94.6 dB/ 98.1 dB and 20μW power consumption at 921 kHz of <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">f</i><sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><b>s</b></sub>, leading to a Schreier figure-of-merit (FOM<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><b>SNDR</b></sub>) of 174.1 dB.