Comparative Analysis of On-Chip FPGA Memory Architectures for Viterbi Decoder Implementation in DVB Systems

High-definition Digital Video Broadcasting (DVB) systems demand high data rates, resulting in increased hardware complexity and power consumption, with the Viterbi decoder (VD) being a key contributor. The substantial memory resources required for these high data rates drive this research, which investigates the impact of diverse static random-access memory (SRAM) architectures on Zynq FPGA and their embedded memory resources, aiming to design power-efficient and less complex Viterbi decoders. Besides, the effect of different memories architectures on the transceiver (Tx-Rx) system has been studied. Viterbi decoder is implemented with different memory architectures on xczu7ev-2ffvc1156: flip flops, distributed RAM, block ram (BRAM), and UltraRAMTM (URAM). BRAM IP from AMD has significantly improved the dynamic power of Viterbi decoder by 97% compared to other available memories. Effectiveness of the employed BRAM is ensured by saving about 50% of the total power of the baseband transceiver system. That Tx-Rx operates at a frequency of 125MHz with a throughput of 62.3 Mbps, a code rate: ½, and 16APSK modulation scheme. Viterbi decoder has achieved a reduction in power compared to sleepy keeper and space time trellis code (STTC) with about 44% and 61% respectively. Functionality of the proposed VD architecture for signal to noise ratio (SNR) of 0 dB at additive white Gaussian noise (AWGN) channel and vector length of 3,264 bits is verified. Hardware validation on ZCU104 based on DVB standard is also done and reported.