Novel Design Approach of Three-Input Logic Implementation in Positive Feedback Source Coupled Logic Style

This paper presents a novel design approach to implement higher fan-in logic functions in the Positive Feedback Source Coupled Logic (PFSCL) style. The existing two design approaches use either NOR gates or fundamental cells that infer the cascading of multiple gates. The new design approach realizes three input logic functions in a single gate and can be further extended for high fan-in circuits. The circuits based on the proposed design approach reduce the cascading of gates by using a new circuit element called a quad-coupled (QC) cell. The design of a 3-input exclusive-OR (XOR3) gate is proposed and compared with the existing XOR3 gates using LT SPICE simulations with PTM 90[Formula: see text]nm CMOS technology parameters. The performance is compared in terms of propagation delay, power consumption, power delay product (PDP), gate count and transistor count. The proposed PFSCL QC XOR3 gate outperforms existing PFSCL XOR3 gates in all performance parameters. It is observed that the proposed PFSCL QC XOR3 gate achieves a maximum and minimum reduction of 81%, 86%, 97% and 87.5% and 73%, 50%, 86%, and 50% in propagation delay, power consumption, PDP and gate count values as compared to the conventional PFSCL XOR3 gate respectively. Furthermore, the Monte Carlo analysis and performance across various process corners is performed to ensure robustness. Additionally, the design example of a full adder is added to demonstrate the versatility and applicability of the proposed QC design approach in complex logic circuitry.