Mismatch and Retention Time Analysis of DRAMs Down to 4 K

Abstract This paper explores the retention time (RT) properties of dynamic random-access memory (DRAM) arrays at cryogenic temperatures (4 K). We provide an in-depth examination of leakage sources to elucidate RT behaviour across different temperatures, and we conduct a study on the mismatch between DRAM cells, highlighting various trade-offs, including cell area, mismatch, retention time, and power consumption. Our findings offer valuable insights for circuit designers working on large-scale quantum computing or superconducting nanowire single-photon detectors (SNSPDs) arrays, especially those aiming to store data at 4 K to avoid the wiring bottleneck associated with outputting each pixel from 4 K to room temperature for data analysis.