Analysis & Implementation of Clock Domain Crossing Techniques Using FIFO Buffers

With the rapid advancement in integrated circuits due to scaling of transistors and efficient technology, modern day CPU are much faster than before. During on-chip communication between several components of a multicore System-on chip, a FIFO buffer can be employed which prevents the loss of data. A FIFO can also be employed at peripherals and at the clock domain crossing in entire SoC. It is mainly classified under two categories - Synchronous and Asynchronous FIFO. Generally, Synchronous FIFO is employed for synchronization of CPU or computer hardware, while Asynchronous FIFOs isolate signals from various clock domains and also buffer the data in case of variations in the data rate or latency. In this paper, some key characteristics and circuit implementation is presented for Asynchronous & Synchronous FIFO through comparative analysis which will help reader in understanding the functioning and specification for FIFO.