LibApprox: A Comprehensive Library for Performance Efficient Approximate Circuits

In digital signal processing and machine learning applications, the demand for efficient hardware-aware computation units is ever-rising. This paper aims to achieve an optimal blend of approximate sub-blocks to evolve a comprehensive library of Pareto optimal approximate hardware-efficient arithmetic circuits of varying error metrics. The study employs Non-dominated Sorting Genetic Algorithm2 (NSGA2), a class of Evolutionary algorithms, for evolving the circuits through approximate sub-blocks of the given list, placing them along the predefined positions for specified iterations. This paper develops a library of hardware-aware, non-dominated static approximate arithmetic circuits, including Adders, Multipliers and Multiply-and-Accumulate (MAC) units of varying bit sizes. The library of circuits is publicly available in Verilog and C models in [1].