C-Element-Based Latch for Flip-Flops: Complete SNU and Partial DNU Tolerance and Resilience to Soft Errors Around Clock Edges

As semiconductor device dimensions and operating voltages continue to scale, soft errors from high-energy cosmic rays pose significant reliability challenges to microelectronic systems. This paper presents a C-element-based latch design for constructing master-slave flip-flops. HSPICE simulations using a 15 nm process design kit demonstrate that connecting the output node of the latch to the input of the next C-element achieves complete Single Node Upset (SNU) tolerance and enhanced Double Node Upset (DNU) tolerance. Experimental results show that while most nodes remain stable under DNU conditions, certain configurations may still experience data flipping. Additionally, excessive charge accumulation at C-element output nodes affects input signals. However, connecting the output to the next C-element input significantly increases the critical charge threshold. Furthermore, the latch and its flip-flop exhibit complete SNU tolerance at input nodes around clock edges.