A Generalized Hardware-Efficient Gabor Wavelet Architecture for Medical Image Processing

Gabor wavelets (GW) are widely adopted for feature extraction and representation, especially in medical image processing. Typically the GW method excels for text-based image analysis, including classification, segmentation, and edge detection tasks. However, the performance of GW technique is limited by the hardware complexity, heavy computations, and large memory access, which seeks a large number of mapped physical resources and heavy compute-power. This paper introduces two highly generic and hardware-efficient multiplier architectures for Gabor image processing applications. The proposed designs were implemented on Kintex-7 FPGA and on silicon using the gpdk-45 nm technology library. Comprehensive architectural implementations and comparisons were conducted against other state-of-the-art solutions. The proposed two designs: i) a parallel multiplexer-based multiplier (PMM), and ii) a serial multiplexer-based multiplier (SMM) demonstrates superior LUT savings of 30.43% and 82.66%, power reduction of 18% and 80% respectively over the most recent SOTA designs. The PMM and SMM designs present the maximum operating frequency of 370 MHz and 357 MHz and on silicon, with footprint savings of 50.07% and 89.70% respectively. The performance of the proposed architecture was evaluated on publicly available datasets, namely NEMA and OASIS. The hardware design files and characteristics are made freely available for further usage to researchers and designers community.