Efficient Digital Architecture of Spiking Encoders for Neuromorphic Accelerators

In Spiking Neural Networks (SNNs), information is transmitted through discrete spikes, making the conversion from real-world signals to spike representations crucial for both encoding efficiency and network performance. This conversion is generally executed using specialized spike encoding algorithms. Among the available methods, rate encoding and temporal encoding are the two most widely utilized encoding schemes in neuromorphic computing. This research assesses and optimizes these encoding schemes, with particular emphasis on their hardware efficiency, data handling capacity, and resilience to noise. Additionally, a novel multiplexed temporal encoding algorithm is developed and tested, demonstrating superior information processing capability and robustness under noisy conditions compared to traditional rate and temporal encoding methods. Evaluation metrics include maximum processing speed, logic utilization, and power consumption on Field-Programmable Gate Array (FPGA), as well as performance in terms of signal reconstruction accuracy under a noisy environment, aiming to enhance SNN performance adaptability and robustness. The results indicate that the multiplexing temporal encoding outperforms other state-of-the-art rate and temporal encoding algorithms in performance and noise robustness across the majority of test samples. It demonstrates a maximum signal reconstruction accuracy improvement of 9.95x across all testing signals compared with other encoding algorithms. Additionally, the proposed rate encoding architectures outperform existing models, showing up to a 3.5x accuracy improvement on all test signals. Furthermore, the proposed TTFS architecture not only demonstrates up to a 5.5x accuracy enhancement over current methods but also reduces logic resource utilization by 57.1%.