Thermal Model Extraction at Chip Boundaries for Thermal Simulation of Chip in a System

With the development of integrated circuits, their functional-ities have been significantly enhanced. However, the increasing power consumption also leads to thermal issues. This work efficiently extracts an equivalent thermal model at the chip boundaries within a system. Attaching the extracted thermal model to boundary surfaces of the chip, we can use fewer thermal grids to simulate chip temperatures but also include the system thermal effect. The experimental results show that the grid reduction is over 76.38% in steady-state thermal simulation and over 51.53% in transient thermal simulation.

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Published
2025-04-23
DOI
https://doi.org/10.1109/isqed65160.2025.11014436
Primary Topic
Parallel Computing and Optimization Techniques
Type
article
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article

Thermal Model Extraction at Chip Boundaries for Thermal Simulation of Chip in a System

Yu‐Min Lee, Bor-Chen Tsai, Kai-Xiang Lin
Parallel Computing and Optimization Techniques
article

Thermal Model Extraction at Chip Boundaries for Thermal Simulation of Chip in a System

Yu‐Min Lee, Bor-Chen Tsai, Kai-Xiang Lin
article en

Abstract

With the development of integrated circuits, their functional-ities have been significantly enhanced. However, the increasing power consumption also leads to thermal issues. This work efficiently extracts an equivalent thermal model at the chip boundaries within a system. Attaching the extracted thermal model to boundary surfaces of the chip, we can use fewer thermal grids to simulate chip temperatures but also include the system thermal effect. The experimental results show that the grid reduction is over 76.38% in steady-state thermal simulation and over 51.53% in transient thermal simulation.

National Yang Ming Chiao Tung University (TW)
Openalex Percentile: Top 89%
Parallel Computing and Optimization Techniques
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