DAPP: Delay Aware Power Prediction

Power analysis done with ideal RTL simulation waveforms using zero-delay analysis is optimistic and does not represent the realistic power dissipation in application specific integrated circuits (ASICs). In order to perform realistic power analysis, commercial electronic design automation (EDA) tools utilize the cell delays and perform delay-aware power analysis. However, this is slow and significantly delays the ASIC tape-out cycle. We present DAPP, a delay-aware power prediction approach using XGBoost regression technique, that can predict the delay-aware power accurately with an R-squared score up to 0.7419 and correlation up to 0.8612 with 1000 estimators. DAPP is validated on ISCAS85 benchmark circuits and provides a speedup of 2.19 × when compared to EDA tool based results, which can improve the overall turnaround time of the ASIC design flow.