RL-Driven Fine-Grained Power Gating for Modern Processors Using Multi-Layer Perceptron Models

This paper introduces an RL-driven algorithm for fine-grained power gating of functional units in superscalar processors. The proposed algorithm leverages a Multi-Layer Perceptron (MLP) neural network as a policy model, trained by a reinforcement learning (RL) agent, to optimize power states across four modes: On, Sleep-on, Sleep-off, and Off. By statically analyzing features extracted from the control flow graph (CFG) and execution profile of the program, the RL-driven model selects the most energy-efficient power states for each functional unit without compromising performance. Traditional power gating techniques often struggle with tradeoffs between minimizing performance loss (wake-up latency) and reducing power consumption, necessitating a reevaluation of power management strategies. Next-generation complex SoC designs at < 7nm technology nodes require a finer granularity approach to effectively manage power states. Our AI-based algorithm provides an optimized trade-off between power efficiency and performance by enabling power gating across multiple power states and selecting the power state that has the effectively least energy-delay product. Additionally, we propose an architectural circuit design for power gating multiple FU's within a superscalar processor, enabling efficient state transitions. Preliminary experimental results show that the proposed AI-based method achieves 10-20% energy savings while improving performance by 1.5% compared to traditional power gating algorithms.