Reinforcement Learning for Testtime Optimization in the Network-on-Chip based Systems

Network on Chip (NoC) serves as a scalable and cost-effective choice for communication between the cores in multicore or manycore systems. As the number of cores on an Integrated Circuit (IC) increases, so does the risk of defects during manufacturing of these multicore systems. This makes the manufacturing test procedures increasingly important. Finding an optimal test schedule from the large-scale system is extremely time-consuming and a complex optimization task. In this paper, we propose a Machine Learning (ML) framework (MAPIC) to enhance the mapping of cores to the Input-Output (IO) pairs in the network, aiming to generate an optimal test schedule for the NoC-based system. Pointer network architecture has been used for generating the mapping solution and ChatGPT 4o has been used to generate <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$NoC$</tex> benchmarks from an IP core repository. The repository contains the cores and their test information from ITC'02 benchmarks. The experimental results indicate the effectiveness of the proposed framework as it outperforms a metaheuristic-based optimization technique.

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Publication Details

Published
2025-04-23
DOI
https://doi.org/10.1109/isqed65160.2025.11014406
Primary Topic
VLSI and Analog Circuit Testing
Type
article
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article

Reinforcement Learning for Testtime Optimization in the Network-on-Chip based Systems

Ashwini Kamath, Kanchan Manna, Aditya Handur-Kulkarni, Himanshu Singh
VLSI and Analog Circuit Testing
article

Reinforcement Learning for Testtime Optimization in the Network-on-Chip based Systems

Ashwini Kamath, Kanchan Manna, Aditya Handur-Kulkarni, Himanshu Singh
article en

Abstract

Network on Chip (NoC) serves as a scalable and cost-effective choice for communication between the cores in multicore or manycore systems. As the number of cores on an Integrated Circuit (IC) increases, so does the risk of defects during manufacturing of these multicore systems. This makes the manufacturing test procedures increasingly important. Finding an optimal test schedule from the large-scale system is extremely time-consuming and a complex optimization task. In this paper, we propose a Machine Learning (ML) framework (MAPIC) to enhance the mapping of cores to the Input-Output (IO) pairs in the network, aiming to generate an optimal test schedule for the NoC-based system. Pointer network architecture has been used for generating the mapping solution and ChatGPT 4o has been used to generate <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$NoC$</tex> benchmarks from an IP core repository. The repository contains the cores and their test information from ITC'02 benchmarks. The experimental results indicate the effectiveness of the proposed framework as it outperforms a metaheuristic-based optimization technique.

Birla Institute of Technology and Science, Pilani (IN)
Openalex Percentile: Top 89%
VLSI and Analog Circuit Testing
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