A Reconfigurable Compute-In-Memory Design with Adaptive Bit-Precision and Power Adjustment

With the successful development of artificial intelligence (AI), Convolutional Neural Networks (CNNs) occupy a large amount of computing time and power consumption in the entire AI computing process. However, in traditional von Neumann architectures, the separation of the computing element and memory leads to the memory-wall problem of memory data transmission bandwidth from memory to processing element when executing multiply-accumulate-based CNN operations. The data transmission time and power consumption all are much higher than the CNN computing part. Therefore, this paper proposes a memory-in-computation design that can flexibly adjust energy usage, achieve high energy efficiency, and support multiple operation frequencies. By controlling the switches of each memory row, unnecessary energy consumption is avoided, leading to a reduction in total power consumption by 15% to 60%. Additionally, by adjusting the pulse width, the charging power consumption of capacitors is reduced by 65% per charge cycle.