DT2HDL: A Binary Decision Tree to HDL Generation Tool

Edge computing devices ideally need to process large amounts of sensor data and execute machine learning models in real-time. Deploying deep learning algorithms can be challenging in energy-constrained nodes with limited computational capacity, when using lightweight classification algorithms is essential. Decision Tree (DT) algorithms require fewer computational resources than Artificial Neural Networks (ANNs) while maintaining similar accuracy. However, implementing DTs on hardware becomes difficult as the number of nodes increases. This work proposes a framework for automatically generating Hardware Description Language (HDL) code for binary decision trees, simplifying their deployment on FPGAs or ASICs. The effectiveness of the DT2HDL tool was evaluated using five distinct datasets: electrical fault detection, electrical fault classification, heart disease, breast cancer, and Iris. Results from both HDL and Python simulations indicate that full-precision decision trees (DTs) and 8-bit quantized DTs achieve the same accuracy levels as artificial neural networks (ANNs) with more than five hidden neurons.