Dynamic Partial Reconfiguration of FPGAs for Energy-Efficient Machine Learning Inference in IoT Systems
This work introduces a dynamic partial reconfiguration (PR) approach for field-programmable gate arrays (FPGAs) to enhance the performance, energy efficiency, and adaptability of IoT systems. By enabling run-time reconfiguration, PR allows flexible allocation of resources for machine learning (ML) tasks, minimizing energy consumption and hardware demands. The method replaces fixed-length floating-point arithmetic with variable bit-width representations, reducing memory usage and computational complexity without sacrificing accuracy. Demonstrated on Graph Convolution Network (GCN)-YOLO models, this approach efficiently handles diverse ML layers while achieving significant improvements in resource utilization, latency, and energy savings. These results establish a scalable framework for real-time edge intelligence in IoT applications.
Authors
- Yuyi Shen (ORCID: https://orcid.org/0000-0002-9792-5397)
- John Kan (ORCID: https://orcid.org/0000-0002-2090-0327)
- Jiachen Xu (ORCID: https://orcid.org/0000-0001-9798-7419)
- Vanessa Chen (ORCID: https://orcid.org/0000-0003-4190-6370)
- Ethan Chen (ORCID: https://orcid.org/0000-0001-9532-3395)
- Junting Deng (ORCID: https://orcid.org/0009-0002-5059-9915)
- C. Cheng (ORCID: https://orcid.org/0009-0002-0426-7848)
Institutions
- Carnegie Mellon University (US)
Publication Details
- Published
- 2025-04-23
- DOI
- https://doi.org/10.1109/isqed65160.2025.11014371
- Primary Topic
- Embedded Systems Design Techniques
- Type
- article
- Field-Weighted Citation Impact
- 0.00
Funders
- National Science Foundation
- Defense Advanced Research Projects Agency
- Office of Naval Research