Obstacle-Aware Synthesis of the Bus Topology Considering Wire Length Minimization

The bus topology, crucial in electronics for multi-device communication, faces challenges with an increasing number of devices and application-specific physical constraints. This work mathematically models bus topological features and obstacle-aware routing constraints in the rectilinear and oc-tilinear routing planes to synthesize the bus topology with minimum total wire length. We implement our rectilinear and octilinear synthesis methods by constructing mixed-integer-linear programming (MILP) models and investigate their performance using eleven commercial inter-integrated circuit <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(\mathrm{I}^{2}\mathrm{C})$</tex> buses on a smartphone motherboard. Experimental results confirm that our methods can efficiently synthesize bus topologies with significantly shorter wire lengths, up to 24.3 %, compared to two baseline methods.