High-Efficiency Threshold-Voltage-Compensated RF Energy Harvester With Gate and Body Biasing Techniques

This article proposes a high-efficiency radio frequency energy harvester (RFEH) design that implements gate and body biasing techniques to decrease the threshold voltage of the transistors in their conduction phases and increase it in their reverse-biasing phases. The proposed scheme simultaneously reduces conduction and leakage losses to achieve higher power conversion efficiency (PCE) for the RFEH. The biasing voltages at the gate and body terminals are generated by amplifying the input signal using passive components, which avoids additional power consumption. To verify the efficacy of the proposed technique, the RFEH system is designed and fabricated using TSMC’s 130 nm standard complementary metal–oxide–semiconductor (CMOS) process for two input power levels: −20 and −10 dBm. The design process of the proposed topology is provided to find the optimum values of passive components of the biasing circuits and the matching network. The measured PCE of the proposed gate-body-biased RFEH systems is 42.9% and 57.9% at input power levels of −20 and −10 dBm, respectively.