Efficient and Scalable Place and Route Methodology for Large-Scale Hierarchical Designs: Achieving Faster Turnaround Time and Predictability

Place and Route of large gate count design in EDA tools is limited by complexity or the size of the design and tool runtime. Multiple methodologies have been developed in the past to limit the complexity of the design and make runtimes more manageable to enable faster turnaround time. Most preferred approach is to partition a large design into multiple sub-chips (hierarchical approach) and reduce the top-level instance count. The hierarchical design is then taken through placement, optimization and routing by the EDA tool wherein sub-chips are abstracted using their physical and timing models. This greatly reduces the complexity of the top-level logic and brings down the runtime of one place and route iteration to 1–2 weeks from multiple weeks. However, the EDA tool requires multiple collaterals such as standard cells and macro timing models, sub-chips timing models, quality timing constraints etc. which may not be available from the very beginning of the execution cycle. Runtime reduction to 1–2 weeks from multiple weeks although is remarkable but is not good enough to enable the designer to run multiple iterations to achieve optimal PPA for the design. Extended runtimes, often spanning in weeks, pose significant challenges to the repeatability and predictability of results. It is crucial for SoC engineers to achieve consistent outcome after every iteration. Even minor changes in collaterals can lead to substantial variations or degradations in results, potentially wasting weeks of runtime. Runtime scalability is another issue wherein with increase in number of sub-chips and overall area of the design, runtime blows up significantly. In this paper an efficient and hybrid top level design closure methodology has been proposed that uses native EDA tool buffering commands but is capable of doing so without the need of timing collaterals. Experiments on different design sizes with this proposed methodology shows a 5-100x reduction in place and route (PD) design cycle time.