A 20-Gb/s 1.4-pJ/bit Wireline Transceiver for Chip-to-Chip Interfaces in 40-nm CMOS

The paper demonstrates a 20-Gb/s transceiver for chip-to-chip communication over silicon interposer. The PLL generates a 20-GHz clock for the transmitter to drive data and for the receiver to recover the clock through the timing recovery loop. Because of the low signal swing, the power compared to regular rail-to-rail CMOS driver is less for the transmitter. The phase-interpolating technique is employed for the clock recovery of the receiver. Implemented in 40-nm CMOS process, the transceiver operates on a 1V supply and demonstrates a power efficiency of 1.4 pJ/bit.