Analysis of Short and Aging Faults in TSVs at the Physical Level with Parametric Variation

The importance of using chiplets and 3D ICs is growing rapidly, driven by the slowing of Moore's Law and the benefits they offer. Advanced packaging of chiplets, and interconnects in 3D ICs are crucial for enhancing computing performance and power efficiency. Hence, Through-Silicon Vias (TSVs) serve as prominent vertical conduits to ensure efficient chip-to-chip communication. The primary objective of this work is to model TSV faults at the material level to observe transmission performance deviations alongside other parametric analyses. We employ Ansys High-Frequency Structure Simulator (HFSS) to design the TSV at the physical level. The reflection coefficient is measured over a 0.1-30 GHz frequency band to observe −15 dB bandwidth for a wide range of lengths <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(30-200 \mu m)$</tex>, radius <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(4-50 \mu m)$</tex>, and insulator thickness <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$(0.2-1.5 \mu m)$</tex>, considering distinct densities. Furthermore, a crack of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$5-15 \mu m$</tex> is introduced in the dielectric layer to implement a short fault, and copper conductance is reduced by 5-30% for different stages of aging faults to evaluate anomalies. Finally, multiple TSVs are incorporated into the design to assess near-end and far-end cross-talk at 15 and <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$30 \mu m$</tex> pitch. Therefore, before developing an equivalent R-L-C circuit for fault detection, it is essential to investigate functionality and faults at the physical level for a more comprehensive understanding.