A PPA- and Security-Aware Physical Design Flow

With the advancement of technology nodes, the division of labor between the design and fabrication of integrated circuits (ICs) has become increasingly specialized. It is difficult for a single company to handle both IC design and IC fabrication on its own. Consequently, multiple companies are likely to be involved. In the process of multiple handovers, there is a potential risk of malicious attacks from untrusted organizations. Therefore, the protection of ICs is of paramount importance. There are existing methods that focus on preventing hardware Trojans from being inserted into physical layouts. However, they usually adopt some geometric information from the layout to evaluate the vulnerability to hardware Trojan insertion, but none of them evaluates the ability to prevent hardware Trojans by conducting real Trojan insertion on the physical layout. In this paper, we propose a physical design flow that considers not only the design quality in terms of power, performance, and area (PPA) but also the design security against layout-level hardware Trojan insertion. The flow consists of two stages (1) Initial Layout Generation and (2) Layout Refinement, while novel techniques, including white space arrangement and timing-aware cell insertion, are developed and integrated into a commercial placement and routing tool to enable the flow. Experimental results demonstrate that our flow is very robust and outperforms the top 3 winners of the ISPD 2023 contest on all benchmarks.