Advanced Leakage Power Reduction Techniques for Low-Power VLSI Design Using Modified Feedback Sleeper Stack (MFSS) for Portable Devices

The increasing need for portable electronic devices with improved energy efficiency has intensified the focus on reducing leakage power in VLSI design, particularly as technology scales to nanoscale CMOS circuits. Leakage currents, which significantly contribute to power dissipation during idle periods, pose a critical challenge to achieving ultra-low power consumption. This paper introduces an advanced approach to leakage power reduction by employing a Modified Feedback Sleeper Stack (MFSS) technique. The proposed method builds on traditional stack-based sleep transistor strategies, integrating innovative feedback mechanisms to enhance efficiency while maintaining favorable area and performance trade-offs. The effectiveness of the MFSS technique is demonstrated through its application to benchmark circuits using various tools in 130nm technology with VT SPICE tools. The assessment emphasizes key parameters like leakage power and power-delay product, showcasing the effectiveness of high-threshold voltage transistors in minimizing static power while maintaining minimal delay impacts. The proposed technique offers a promising solution for energy-efficient VLSI design, enabling significant leakage power mitigation without compromising performance. It provides a valuable tool for designing next-generation portable devices where battery longevity and energy efficiency are paramount concerns.