Cross-Layer EM Fault Injection Assessment Framework

Threats posed by both power and Electromagnetic (EM) fault injection (FI) are widely investigated in integrated circuit (IC) security. These fault injection attacks exploit the physical behavior of transistors to induce unintended behaviors in circuits. In recent years, researchers have begun to model and simulate both EM and power fault injection and their impacts. However, most research fails to perform cross-domain analysis from the transistor level to the gate level, then to the RT level, and finally tot he system level. Therefore, w e propose a cross-layer power and EMFI evaluation framework that helps to assess the impact of EM/Power FI from the bottom up. Our framework takes information from all layers in the IC design process into consideration and uses SPICE simulation to emulate the fault induced by EM/Power spikes. We further propose EMFI register bitflip probability equations to quantify, characterize, and verify our results. Finally, we prove the effectiveness of our approach using a range of system-level benchmarks, and our register bitflip probability matches closely with the SPICE simulation result.