A 1.2GHz High Operational Frequency, High Energy Efficiency, Hybrid Segmented Computation with Pre-charge Free In-Memory-Search TCAM Design

With the rapid development of artificial intelligence (AI), people have become increasingly reliant on its ability to address most issues in real time. However, the significant increase in the data that AI needs to learn and process has led to daunting computational and storage power consumption. Consequently, learning from a small number of samples while maintaining high accuracy has become a critical challenge. Few-shot learning and memory-augmented neural networks (MANN) are notable for their capability of rapid learning. By adopting memory units to store and retrieve large amounts of feature, these approaches can quickly complete new tasks with minimal training samples. Memory-augmented neural networks, combined with ternary content-addressable memory (TCAM), achieve high accuracy in sample training. By performing comparison and matching directly within memory, the frequency of CPU/GPU accesses can be reduced, further mitigating data transfer latency and improving model training efficiency[6]. Hence, This paper proposes a high-frequency, energy-efficient, high-bit-supported in-memory search design. The proposed circuit is an innovative in-memory search architecture that achieves high operational frequency and energy efficiency through the implementation of hybrid segment computation combined with a novel pre-charge-free SRAM-based TCAM. To fabricate the design, it has been implemented using TSMC's standard 28nm CMOS process, achieving FoM up to 2000, outperforming the most advanced in-memory search circuit chips available today.