Power and Area-Efficient ECC Processor with Sequential Recursive Polynomial Multiplier Implementation

Elliptic curve cryptography (ECC) is a unique and efficient public-key cryptography method where polynomial multiplication is the primary operation. Thus, ECC efficiency depends largely on effective polynomial multiplier implementation. This work presents a hardware-efficient ECC processor with a clocked data-path using an M-term Hybrid Karatsuba multiplier for GF(2<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">233</sup>) Montgomery multiplication. The proposed design was implemented on a Kintex UltraScale FPGA and synthesized with a 45 nm library using Cadence Genus, with the sequential multiplier data path integrated into the ECC processor. The M-Term Non-Homogeneous Overlap-Free Karat-sub a Multiplier (MNHOKA) and Composite M-Term Overlap-Free Karatsuba-like Multiplier (CMOKA) multipliers, integrated into ECC processors, achieved top hardware efficiency on FPGA and silicon, surpassing all other variants and SOTA multipliers. The clocked MNHOKA-adopted ECC processor achieved LUT savings of 56.11% and a Figure-of-Merit (FoM) improvement of 74.73% in FPGA over the best SOTA design. On silicon, the sequential design of Overlap-Free Karatsuba Multiplier (OKA) incorporated ECC processor exhibited maximum footprint savings of 45.70% and clocked MNHOKA incorporated ECC processor exhibited maximum power saving of 73.00% over the best SOTA design. The innovative and hardware-efficient ECC accelerator design files are made freely available for further usage to the designers and engineering community.