Loop Bandwidth Extension Technique for FVF -Based Low Drop-Out Regulator

This paper proposes an output capacitor-free analog low-dropout regulator (LDO) suitable for memory circuits. The circuit architecture adopts a flipped voltage follower (FVF) configuration. The local loop incorporates super source follower (SSF) and gain boosting stage (GBS) circuits to extend loop bandwidth and enhance loop gain. This LDO is implemented in a 90nm process. In simulation result, with an input voltage of 1.05V, it maintains an output voltage of 1V and supports output load currents ranging from 100uA to 40mA. Under load switching conditions with a load step time of 10ns, the undershoot voltage is 140mV, settling time is 550ns, and quiescent current under heavy load conditions is 45uA.