Design of Hardware-Efficient Inexact Multiplier Using Evolutionary Algorithm Factored by Multi-Variate Approximation

In the current era of technology, multipliers are integral to various hardware accelerators, making the design of efficient multipliers increasingly essential. This research introduces a novel approach to designing hardware-efficient inexact multipliers by applying multiple approximation strategies guided by a multi-objective evolutionary optimization algorithm. Using the Non-dominated Sorting Genetic Algorithm II (NSGA-II), we explore an extensive design space for 8-bit signed and unsigned multipliers, optimizing bit truncation, approximation, and compressor configurations. Our methodology demonstrates substantial improvements in hardware metrics, with reductions in power consumption by 12–25%, footprint utilization by 18–30%, and critical path delay by 14–18% over exact multipliers across a range of applications, including image processing and neural network computations. When compared with a group of SOTA inexact multiplier, the proposed multipliers exhibit a range of 2% to 5% delay improvement, 5% to 15% footprint savings, 5% to 15% power savings with comparable error metrics and SSIM quality index. The resulting Pareto-optimal solutions evolved from multi-objective evolutionary algorithm run factored with multiple approximation strategies provide a variety of multiplier designs that strike a balance between computational accuracy and hardware efficiency, advancing approximate computing and offering designers flexible, application-specific options for error-tolerant hardware accelerators.