Robust and Efficient NAND-Like TST-MRAM with Parallel Write/Read Operations and Reconfigurable PUF Mode

This paper presents an optimized NAND-like toggle spin torques magnetic random-access memory (TST-MRAM) for high-density cache applications, achieving significant advancements in reliability and power efficiency. By decoupling the spin-orbit torque (SOT) and the spin-transfer torque (STT) currents, the proposed design tackles the reliability challenges associated with parallel write operations and enhances the operational feasibility. A dual-end write method is introduced to effectively minimize SOT current interference during the STT phase, resulting in improved write reliability and a reduction in the maximum write error rate from 17.6% to 0. Furthermore, a dual-end read method is proposed to mitigate potential offsets caused by the states of neighboring devices. Coupled with the proposed optimized reference circuit design, these measures significantly improve the read reliability. Additionally, leveraging the parallel random number generation capability of NAND-like TST-MRAM, a reconfigurable physical unclonable function (PUF) mode is introduced to reduce the average bit-cell area by 37.5% and reconfiguration power consumption by approximately 70% compared to conventional designs.