A Comprehensive Approach to Characterizing $V_{T}$ Miscorrelation Derates for Physical Design and Timing Signoff

Die-to-Die (D2D) process variation which affects circuit performance, is typically handled through analysis at multiple performance corners. Performance-corner approach assumes that all devices are perfectly correlated under D2D variation. As a result, effects like partial miscorrelation between V<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</inf> types, that is seen in recent process nodes cannot be modeled through performance corners. Partial miscorrelations can lead to circuit marginalities and affect clock-vs-data race conditions and is hence modeled through additional timing derates. While Electronic Design Automation (EDA) tools allow timing analysis by speeding up or slowing down target cells based on the derates, the responsibility of derate characterization is often left to design-houses or the foundry. In this work, we introduce a robust methodology and flow for accurately characterizing <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$V_{T}$</tex> miscorrelation derates for use in sign-off flows. Inappropriate derates lead to over-design or yield loss. We employ detailed statistical analysis to derive <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$V_{T}$</tex> miscorrelation derates that consider partial correlation w.r.t other <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$V_{T}$</tex> devices, resulting in up to 15% reduction compared to industry standard methods, improving yield recovery by pessimism reduction.