A Novel Full Adder Design Using Hybrid Memristor Ratioed Logic

We propose a novel hybrid memristor ratioed logic (MRL) based full adder design. We implement four versions of the hybrid full adder ranging from 10T4R to 16T4R. The adders employ hybrid MRL XOR gates and demonstrate varying area, energy and delay tradeoffs. A proposed pull-up stack based hybrid MRL 4T2R XOR gate is shown to enable reliable carry signal propagation thereby alleviating the need for buffer insertion between intermediate carry stages in a 32-bit adder design. The 14T2R adder version which utilizes the 4T2R for its sum module demonstrates an enhanced normalized area-energy-delay product by upto 2.9X compared to the other adder versions. We study the effect of memristor process variations on the adder performance in convolution applications where addition is a fundamental operation. We demonstrate less than 0.5% drop for the test accuracy of a convolutional neural network classification of the MNIST dataset in the presence of 20% memristor coefficient of variation. We also demonstrate high resolution of 44 dB peak signal to noise ratio for image convolution for memristor coefficient of variation of upto 30% for the high resistive states. Finally, we assess the image convolution quality under the extreme scenario of memristor stuck-at-faults.