A Time-Borrowing Method for High-Performance Bundled-Data Asynchronous Circuits

Asynchronous circuits are increasingly being used in Very Large Scale Integration (VLSI) to address power consumption challenges. The performance of existing asynchronous circuits is still constrained by critical paths, and the phase shift induced by the asynchronous handshake logic exacerbates the adverse effects caused by critical path. Latches have the potential to address this issue due to their timing borrowing characteristics, and they consume lower power compared to flip-flops (FFs). However, most existing asynchronous circuits are only geared towards flip-flop-based designs and cannot fully capitalize on the advantages of latches. In this article, we propose a time-borrowing method for asynchronous circuits, including a novel dual-phase lightweight asynchronous controller (DPLAC) and a margin-aware asynchronous control method, which can fully exploit the low-power and time-borrowing characteristics of latches. To verify this method, we designed an asynchronous RISC-V processor with dual-phase latches on the TSMC 65-nm process. Compared to its synchronous version, when operating at the extreme frequency, the asynchronous processor achieves a 15.8% increase in speed (from 227.3 to 263.2MHz) while reducing power consumption by 28.71%.