Meta-Heuristic Optimization for Designing Error Diluted Weight Stationary Approximate Systolic Array Architecture

Systolic Arrays (SA) are hardware accelerators designed for performing general matrix multiplication (GEMM) operations. They are most effectively utilized as hardware accelerators for training and running the Convolution-based Neural Networks (CNNs). These accelerators are expected to be made more hardware efficient by effectively employing inexact processing elements (PEs). Incorporating approximate multipliers in SAs causes a deviation from the exact result, and the inaccuracy widens when applied for convolution operations across the layers. Adopting positive and negative error distributed multipliers selectively as PEs in a SA is expected to minimize the errors over the successive accumulation of multiplicative operations for a given convolution channel. This paper proposes a meta-heuristic multi-objective-based evolutionary framework for engineering the most optimal SA architecture incorporating positive and negative error-distributed multipliers, for realizing convolution filter channels of CNN. The proposed approach achieves both hardware benefits and maintains high output quality towards extracting adequate features, for yielding reliable CNN results when compared against other state-of-the-art approximate SA configurations. In this paper, SA configuration for three different filter channels picked from first layer of VGG-11 CNN model is presented. The framework and hardware design files are made freely available for further usage to the researchers' and designers' community.